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M36W0R6040T1 M36W0R604BT1
64 Mbit (4 Mb x16, Multiple Bank, Burst) Flash memory and 16 Mbit (1 Mb x16) PSRAM, multi-chip package
Features
Multi-chip package - 1 die of 64 Mbit (4 Mb x 16) Flash memory - 1 die of 16 Mbit (1 Mb x 16) Pseudo SRAM Supply voltage - VDDF = VDDP = VDDQ = 1.7 V to 1.95 V Low power consumption Electronic signature - Manufacturer Code: 20h - Device Code (top flash configuration), M36W0R6040T1: 8810h - Device Code (bottom flash configuration), M36W0R604BT1: 8811h ECOPACK(R) packages available
FBGA

Stacked TFBGA88 (ZAQ) 8 x 10 mm
Block locking - All blocks locked at Power-up - Any combination of blocks can be locked - WPF for Block Lock-Down Security - 128-bit user programmable OTP cells - 64-bit unique device number Common Flash Interface (CFI) 100 000 program/erase cycles per block
Flash memory
Programming time - 8 s by Word typical for Fast Factory Program - Double/Quadruple Word Program option - Enhanced Factory Program options Memory blocks - Multiple Bank Memory Array: 4 Mbit Banks - Parameter Blocks (Top or Bottom location) Synchronous / Asynchronous Read - Synchronous Burst Read mode: 66 MHz - Asynchronous/ Synchronous Page Read mode - Random Access: 70 ns Dual operations - Program Erase in one Bank while Read in others - No delay between Read and Write operations

PSRAM

Access time: 70 ns Low standby current: 110 A Deep power down current: 10 A
November 2007
Rev 0.3
1/22
www.numonyx.com 1
Contents
M36W0R6040T1, M36W0R604BT1
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 Address Inputs (A0-A19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address Inputs (A20-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Input/Output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash Latch Enable (LF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash Clock (KF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash Wait (WAITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Chip Enable (E1P
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PSRAM Chip Enable (E2P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VDDF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VDDP supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VPPF program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 4 5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/22
M36W0R6040T1, M36W0R604BT1
Contents
6 7 8
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
List of tables
M36W0R6040T1, M36W0R604BT1
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Stacked TFBGA88 8 x 10 mm - 8 x 10 ball array, 0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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M36W0R6040T1, M36W0R604BT1
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Stacked TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch, package outline. . 19
5/22
Description
M36W0R6040T1, M36W0R604BT1
1
Description
The M36W0R6040T1 and M36W0R604BT1 combine two memory devices in a multi-chip package:

a 64-Mbit, Multiple Bank Flash memories, the M58WR064HT/B a 16-Mbit Pseudo SRAM, the M69AR024B. Recommended operating conditions do not allow more than one memory to be active at the same time.
The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58WR064HTB and M69AR024B datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. The memory is offered in a Stacked TFBGA88 (8 x 10 mm, 8 x 10 ball array, 0.8 mm pitch) package. In order to meet environmental requirements, Numonyx offers the M36W0R6040T1 and M36W0R604BT1 in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. The memory is supplied with all the bits erased (set to `1').
6/22
M36W0R6040T1, M36W0R604BT1 Figure 1. Logic diagram
VDDQ VDDF 22 A0-A21 DQ0-DQ15 EF GF WF RPF WPF LF KF E1P GP WP E2P UBP LBP M36W0R6040T1 M36W0R6040B1 WAITF VPPF VDDP 16
Description
VSS
Ai11080b
7/22
Description Table 1.
A0-A19 DQ0-DQ15 VDDF VDDQ VPPF VSS VDDP NC DU
M36W0R6040T1, M36W0R604BT1 Signal names
Common Address Inputs Common Data Input/Output Flash Memory Power Supply Common Flash and PSRAM Power Supply for I/O Buffers Common Flash Optional Supply Voltage for Fast Program & Erase Ground PSRAM Power Supply Not Connected Internally Do Not Use as Internally Connected
Flash memory control functions A21-A20 LF EF GF WF RPF WPF KF WAITF Address Inputs for the Flash memory only Latch Enable input Chip Enable input Output Enable input Write Enable input Reset input Write Protect input Burst Clock Wait Data in Burst Mode
PSRAM control functions E1P GP WP E2P UBP LBP Chip Enable input Output Enable input Write Enable input Power-down input Upper Byte Enable input Lower Byte Enable input
8/22
M36W0R6040T1, M36W0R604BT1 Figure 2. TFBGA connections (top view through package)
1 2 3 4 5 6 7 8
Description
A
DU
DU
DU
DU
B
A4
A18
A19
VSS
VDDF
NC
A21
A11
C
A5
LBP
NC
VSS
NC
KF
NC
A12
D
A3
A17
NC
VPPF
WP
EP
A9
A13
E
A2
A7
NC
WPF
LF
A20
A10
A15
F
A1
A6
UBP
RPF
WF
A8
A14
A16
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAITF
NC
H
GP
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
NC
J
NC
GF
DQ9
DQ11
DQ4
DQ6
DQ15
VDDQ
K
EF
NC
NC
NC
VDDP
NC
VDDQ
E2P
L
VSS
VSS
VDDQ
VDDF
VSS
VSS
VSS
VSS
M
DU
DU
DU
DU
AI08525
9/22
Signal descriptions
M36W0R6040T1, M36W0R604BT1
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connect-ed to this device.
2.1
Address Inputs (A0-A19)
Addresses A0-A19 are common inputs for the Flash Memory and PSRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Flash memory Program/Erase Controller, and they select the cells to access in the PSRAM. The Flash memory is accessed through the Chip Enable signal (EF) and through the Write Enable (WF) signal, while the PSRAM is accessed through two Chip Enable signals (E1P and E2P) and the Write Enable signal (WP).
2.2
Address Inputs (A20-A21)
Addresses A20-A21 are inputs for the Flash memory component only. The Flash memory is accessed through the Chip Enable signals (EF) and through the Write Enable (WF) signal.
2.3
Data Input/Output (DQ0-DQ15)
For the Flash memory, the Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. For the PSRAM, the Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UBP) is driven Low. Likewise, the Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LBP) is driven Low.
2.4
Flash Chip Enable (EF)
The Chip Enable inputs activate the memory control logics, input buffers, decoders and sense amplifiers. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level.
2.5
Flash Output Enable (GF)
The Output Enable pins control data outputs during Flash memory Bus Read operations.
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M36W0R6040T1, M36W0R604BT1
Signal descriptions
2.6
Flash Write Enable (WF)
The Write Enable controls the Bus Write operation of the Flash memories' Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.
2.7
Flash Write Protect (WPF)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the LockedDown blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (Refer to Lock Status Table in M58WR064HT/B datasheet).
2.8
Flash Reset (RPF)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to the M58WR064HT/B datasheet, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to the M58WR064HT/B datasheet).
2.9
Flash Latch Enable (LF
Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is Low, VIL, and it is inhibited when Latch Enable is High, VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.
2.10
Flash Clock (KF)
The Clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is don't care during Asynchronous Read and in write operations.
2.11
Flash Wait (WAITF)
WAIT is a Flash output signal used during Synchronous Read to indicate whether the data on the output bus are valid. This output is high impedance when Flash Chip Enable is at VIH or Flash Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable.
11/22
Signal descriptions
M36W0R6040T1, M36W0R604BT1
2.12
PSRAM Chip Enable (E1P
When asserted (Low), the Chip Enable, E1P, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When deasserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode.
2.13
PSRAM Chip Enable (E2P)
The Chip Enable, E2P, puts the device in Deep Power-down mode when it is driven Low. This is the lowest power mode.
2.14
PSRAM Output Enable (GP)
The Output Enable, GP, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus.
2.15
PSRAM Write Enable (WP)
The Write Enable, WP, controls the Bus Write operation of the memory.
2.16
PSRAM Upper Byte Enable (UBP)
The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.17
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0DQ7) to or from the lower part of the selected address during a Write or Read operation.
2.18
VDDF supply voltage
VDDF provides the power supply to the internal core of the Flash memory component. It is the main power supplies for all Flash memory operations (Read, Program and Erase).
2.19
VDDP supply voltage
The VDDP Supply Voltage supplies the power for all operations (Read or Write) and for driving the refresh logic, even when the device is not being accessed.
12/22
M36W0R6040T1, M36W0R604BT1
Signal descriptions
2.20
VDDQ supply voltage
VDDQ provides the power supply for the Flash Memory and PSRAM I/O pins. This allows all Outputs to be powered independently of the Flash Memory and PSRAM core power supplies: VDDF and VDDP, respectively.
2.21
VPPF program supply voltage
VPPF is both a Flash Memory control input and a Flash Memory power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQ) VPPF is seen as a control input. In this case a voltage lower than VPPLKF gives an absolute protection against Program or Erase, while VPPF > VPP1F enables these functions (see the M58WR064HT/B datasheet for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If VPPF is in the range of VPPHF it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed.
2.22
VSS ground
VSS is the common ground reference for all voltage measurements in the Flash (core and I/O Buffers) and PSRAM chips.
Note:
Each Flash memory device in a system should have its supply voltage (VDDF) and the program supply voltage VPPF decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents.
13/22
Functional description
M36W0R6040T1, M36W0R604BT1
3
Functional description
The Flash memory and PSRAM components have separate power supplies but share the same grounds. They are distinguished by three Chip Enable inputs: EF for the Flash memory and E1P and E2P for the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The most common example is simultaneous read operations on the Flash memory and the PSRAM which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device. Figure 3. Functional block diagram
VDDF VPPF VDDQ
A20-A21
EF GF WF LF KF RPF A0-A19 WPF
64 Mbit Flash Memory
WAITF
DQ0-DQ15
VDDP
E1P GP WP E2P UBP LBP 16 Mbit PSRAM
VSS
AI08449
14/22
M36W0R6040T1, M36W0R604BT1 Table 2. Main operating modes(1)
EF VIL VIL VIL VIL VIH X GP VIL VIH X WP VIH VIL VIH LF VIL
(3)
Functional description
Operation Flash Read Flash Write Flash Address Latch Flash Output Disable Flash Standby Flash Reset PSRAM Read
RPF WAITF(2) E1P E2P VIH VIH VIH VIH VIH VIL Hi-Z Hi-Z VIL VIL VIL VIH VIH VIH VIH VIL
GP
WP
UBP LBP
DQ15-DQ0 Flash Data Out
VIL(3) VIL X X X
PSRAM must be disabled
Flash Data In Flash Data Out or Hi-Z(4) Flash Hi-Z
VIH VIH X X X X
Any PSRAM mode is allowed
Flash Hi-Z Flash Hi-Z
Flash Memory must be disabled PSRAM Write Output Disable PSRAM Standby PSRAM Deep Power-Down
1. X = Don't care.
VIL VIH VIH X X
VIH VIL VIH X X
VIL VIL X X X
VIL VIL X X X
PSRAM data out PSRAM data in PSRAM Hi-Z PSRAM Hi-Z PSRAM Hi-Z
Any Flash mode is allowed.
VIH X
2. WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR064HT/B datasheet for details. 3. LF can be tied to VIH if the valid address has been previously latched. 4. Depends on GF.
15/22
Maximum rating
M36W0R6040T1, M36W0R604BT1
4
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 3.
Symbol TA TBIAS TSTG VIO VDDF VDDQ VDDP VPPF IO tVPPFH
Absolute maximum ratings
Value Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Flash Memory Core Supply Voltage Input/Output Supply Voltage PSRAM Supply Voltage Flash Memory Program Voltage Output Short Circuit Current Time for VPPF at VPPFH -30 -40 -65 -0.5 -0.2 -0.2 -0.2 -0.2 Max 85 125 155 VDDQ+0.6 2.45 2.45 3.3 14 100 100 C C C V V V V V mA hours Unit
16/22
M36W0R6040T1, M36W0R604BT1
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4., Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and AC measurement conditions
Flash memory Parameter Min VDDF Supply Voltage VDDP Supply Voltage VDDQ Supply Voltage
VPPF Supply Voltage (Factory environment) VPPF Supply Voltage (Application environment)
PSRAM Unit Min - 1.7 - - - -30 50 Max - 1.95 - - - 85 V V V V V C pF ns 0 to VDDP VDDP/2 V V
Max 1.95 - 1.95 12.6 VDDQ +0.4 85 30 5
1.7 - 1.7 11.4 -0.4 -40
Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
0 to VDDQ VDDQ/2
Figure 4.
AC measurement I/O waveform
VDDQ VDDQ/2 0V
AI06161
17/22
DC and AC parameters Figure 5. AC measurement load circuit
M36W0R6040T1, M36W0R604BT1
VDDQ
VDDF
VDDQ 16.7k DEVICE UNDER TEST
0.1F 0.1F
CL
16.7k
CL includes JIG capacitance
AI08364
Table 5.
Symbol CIN COUT
Device capacitance(1)
Parameter Input Capacitance Output Capacitance Test condition VIN = 0V VOUT = 0V Min Max 12 15 Unit pF pF
1. Sampled only, not 100% tested.
Please refer to the M58WR064HT/B and M69AR024B datasheets for further DC and AC characteristics values and illustrations.
18/22
M36W0R6040T1, M36W0R604BT1
Package mechanical
6
Package mechanical
Figure 6. Stacked TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch, package outline
D D1
e SE E E2 E1 b BALL "A1"
ddd FE FE1 A A1 FD SD A2
BGA-Z42
1. Drawing is not to scale.
Table 6.
Stacked TFBGA88 8 x 10 mm - 8 x 10 ball array, 0.8 mm pitch, package mechanical data
millimeters inches Max 1.200 0.200 0.850 0.350 8.000 5.600 0.100 10.000 7.200 8.800 0.800 1.200 1.400 0.600 0.400 0.400 - - 9.900 10.100 0.3937 0.2835 0.3465 0.0315 0.0472 0.0551 0.0236 0.0157 0.0157 - - 0.3898 0.300 7.900 0.400 8.100 0.0335 0.0138 0.3150 0.2205 0.0039 0.3976 0.0118 0.3110 0.0157 0.3189 0.0079 Typ Min Max 0.0472
Symbol Typ A A1 A2 b D D1 ddd E E1 E2 e FD FE FE1 SD SE Min
19/22
Part numbering
M36W0R6040T1, M36W0R604BT1
7
Part numbering
Table 7.
Example: Device type M36 = Multi-chip package (Multiple Flash + RAM) Flash 1 architecture W = Multiple Bank, Burst mode Flash 2 architecture 0 = none present Operating voltage R = VDDF = VDDQ =VDDP = 1.7 V to 1.95 V Flash 1 density 6 = 64 Mbit Flash 2 density 0 = none present RAM 1 density 4 = 16 Mbit RAM 0 density 0 = none present Parameter blocks location T = Top Boot Block Flash B = Bottom Boot Block Flash Product version 1 = 90 nm Flash technology, 70 ns; 0.18 m RAM, 70 ns speed Package ZAQ = Stacked TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch Option E = ECOPACK(R) Package, Standard Packing F = ECOPACK(R) Package, Tape & Reel Packing
Ordering information scheme
M36 W 0 R 6 0 4 0 T 1 ZAQ E
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you.
20/22
M36W0R6040T1, M36W0R604BT1
Revision history
8
Revision history
Table 8.
Date 08-June-2005
Document revision history
Version 0.1 First Issue. Document status promoted from Target Specification to full Datasheet. Package is ECOPACK(R) compliant. DC characteristics of Flash memory and PSRAM components removed (for further details please refer to the M58WR064HT/B and M69AR024B datasheets. Small text changes. Applied Numonyx branding. Revision Details
18-Jan-2007
0.2
14-Nov-2007
0.3
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M36W0R6040T1, M36W0R604BT1
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